// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2022 liujuan1@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN8IW11_H_
#define _DT_BINDINGS_CLK_SUN8IW11_H_

#define CLK_PLL_CPUX		0
#define CLK_PLL_AUDIO_1X	1
#define CLK_PLL_AUDIO_4X	2
#define CLK_PLL_AUDIO_8X	3
#define CLK_PLL_AUDIO		4
#define CLK_PLL_VIDEO0_1X	5
#define CLK_PLL_VIDEO0_2X	6
#define CLK_PLL_VE		7
#define CLK_PLL_DDR0		8
#define CLK_PLL_PERIPH0_2X	9
#define CLK_PLL_PERIPH0_1X	10
#define CLK_PLL_PERIPH1_2X	11
#define CLK_PLL_PERIPH1_1X	12
#define CLK_PLL_VIDEO1_1X	13
#define CLK_PLL_VIDEO1_2X	14
#define CLK_PLL_SATA		15
#define CLK_PLL_GPU		16
#define CLK_PLL_MIPI		17
#define CLK_PLL_DE		18
#define CLK_PLL_DDR1		19
#define CLK_CPUX		20
#define CLK_AXI			21
#define CLK_PLL_PERIPHAHB0	22
#define CLK_AHB1		23
#define CLK_APB1		24
#define CLK_APB2		25
#define CLK_USB_OHCI2		26
#define CLK_USB_OHCI1		27
#define CLK_USB_OHCI0		28
#define CLK_BUS_EHCI2		29
#define CLK_BUS_EHCI1		30
#define CLK_BUS_EHCI0		31
#define CLK_BUS_OTG		32
#define CLK_BUS_SATA		33
#define CLK_BUS_SPI3		34
#define CLK_BUS_SPI2		35
#define CLK_BUS_SPI1		36
#define CLK_BUS_SPI0		37
#define CLK_BUS_HSTMR		38
#define CLK_BUS_TS		39
#define CLK_BUS_EMAC		40
#define CLK_BUS_DRAM		41
#define CLK_BUS_NAND		42
#define CLK_BUS_MMC3		43
#define CLK_BUS_MMC2		44
#define CLK_BUS_MMC1		45
#define CLK_BUS_MMC0		46
#define CLK_BUS_DMA		47
#define CLK_BUS_CE		48
#define CLK_BUS_MIPIDSI		49
#define CLK_BUS_TCONTOP		50
#define CLK_BUS_TCONTV1		51
#define CLK_BUS_TCONTV0		52
#define CLK_BUS_TCONLCD1	53
#define CLK_BUS_TCONLCD0	54
#define CLK_BUS_TVDTOP		55
#define CLK_BUS_TVD3		56
#define CLK_BUS_TVD2		57
#define CLK_BUS_TVD1		58
#define CLK_BUS_TVD0		59
#define CLK_BUS_GPU		60
#define CLK_BUS_GMAC		61
#define CLK_BUS_TVETOP		62
#define CLK_BUS_TVE1		63
#define CLK_BUS_TVE0		64
#define CLK_BUS_DE		65
#define CLK_BUS_HDMI1		66
#define CLK_BUS_HDMI0		67
#define CLK_BUS_CSI1		68
#define CLK_BUS_CSI0		69
#define CLK_BUS_DI		70
#define CLK_BUS_MP		71
#define CLK_BUS_VE		72
#define CLK_BUS_DAUDIO2		73
#define CLK_BUS_DAUDIO1		74
#define CLK_BUS_DAUDIO0		75
#define CLK_BUS_KEYPAD		76
#define CLK_BUS_THS		77
#define CLK_BUS_IR1		78
#define CLK_BUS_IR0		79
#define CLK_BUS_PIO		80
#define CLK_BUS_AC97		81
#define CLK_BUS_SPDIF		82
#define CLK_BUS_AC_DIG		83
#define CLK_BUS_UART7		84
#define CLK_BUS_UART6		85
#define CLK_BUS_UART5		86
#define CLK_BUS_UART4		87
#define CLK_BUS_UART3		88
#define CLK_BUS_UART2		89
#define CLK_BUS_UART1		90
#define CLK_BUS_UART0		91
#define CLK_BUS_TWI4		92
#define CLK_BUS_PS2_1		93
#define CLK_BUS_PS2_0		94
#define CLK_BUS_SCR		95
#define CLK_BUS_TWI3		96
#define CLK_BUS_TWI2		97
#define CLK_BUS_TWI1		98
#define CLK_BUS_TWI0		99
#define CLK_BUS_DBGSYS		100
#define CLK_SDMM2_MOD		101
#define CLK_THS			102
#define CLK_NAND		103
#define CLK_MMC0		104
#define CLK_MMC1		105
#define CLK_MMC2		106
#define CLK_MMC3		107
#define CLK_TS			108
#define CLK_CE			109
#define CLK_SPI0		110
#define CLK_SPI1		111
#define CLK_SPI2		112
#define CLK_SPI3		113
#define CLK_DAUDIO0		114
#define CLK_DAUDIO1		115
#define CLK_DAUDIO2		116
#define CLK_AC97		117
#define CLK_SPDIF		118
#define CLK_KEYPAD		119
#define CLK_SATA		120
#define CLK_12M_FROM_48M	121
#define CLK_12M_FROM_24M	122
#define CLK_12M_FROM_32K	123
#define CLK_32K_FROM_24M	124
#define CLK_OHCI2_12M		125
#define CLK_OHCI1_12M		126
#define CLK_OHCI0_12M		127
#define CLK_USBPHY2_GATE	128
#define CLK_USBPHY1_GATE	129
#define CLK_USBPHY0_GATE	130
#define CLK_IR0			131
#define CLK_IR1			132
#define CLK_DRAM		133
#define CLK_DI_GATE		134
#define CLK_MP_GATE		135
#define CLK_TVD_GATE		136
#define CLK_TS_GATE		137
#define CLK_CSI1_GATE		138
#define CLK_CSI0_GATE		139
#define CLK_VE_GATE		140
#define CLK_DE			141
#define CLK_DE_MP		142
#define CLK_TCON_LCD0		143
#define CLK_TCON_LCD1		144
#define CLK_TCON_TV0		145
#define CLK_TCON_TV1		146
#define CLK_DEINTERLACE		147
#define CLK_CSI_MISC		148
#define CLK_CSI_SCLK		149
#define CLK_CSI_MCLK0		150
#define CLK_VE			151
#define CLK_AC_DIGITAL_GATE	152
#define CLK_AVS_GATE		153
#define CLK_HDMI		154
#define CLK_HDMI_DDC_GATE	155
#define CLK_MBUS		156
#define CLK_RMII_GATE		157
#define CLK_EPIT_GATE		158
#define CLK_MIPI_DSI		159
#define CLK_TVE0		160
#define CLK_TVE1		161
#define CLK_TVD0		162
#define CLK_TVD1		163
#define CLK_TVD2		164
#define CLK_TVD3		165
#define CLK_GPU			166
#define CLK_OUTA		167
#define CLK_OUTB		168

#define CLK_MAX_NO		CLK_OUTB

#endif /* _DT_BINDINGS_CLK_SUN8IW11_H_ */
